This invention is in the field of solid-state memories. Embodiments of this invention are more specifically directed to the sensing of stored data states in one-time programmable non-volatile memory.
Non-volatile solid-state read/write memory devices are commonplace in many modern electronic systems, particularly in portable electronic devices and systems. Conventional types of non-volatile solid-state memory devices include those referred to as electrically programmable read-only memory (EPROM) devices. Modern EPROM memory cells include one or more “floating-gate” transistors that store the data state. In a general sense, these floating-gate transistors are “programmed” by the application of a bias that enables holes or electrons to tunnel or be injected through a thin dielectric film onto an electrically isolated transistor gate element, which is the floating gate of the transistor. This trapped charge on the floating gate will modulate the apparent threshold voltage of the memory cell transistor, as compared with the threshold voltage with no charge trapped on the floating gate. This difference in threshold voltage can be detected by sensing the resulting difference in source-drain conduction, under normal transistor bias conditions, between the programmed and unprogrammed states. Some EPROM devices are “erasable” in that the trapped charge can be removed from the floating gate, for example by exposure of the memory cells to ultraviolet light (such memories referred to as “UV EPROMS”) or by application of a particular electrical bias condition that enables tunneling of the charge from the floating gate (such memories referred to as electrically-erasable or electrically-alterable, i.e., EEPROMs and EAPROMS, respectively). “Flash” memory devices are typically realized by EEPROM memory arrays in which the erase operation is applied simultaneously to a “block” of memory cells.
Because of the convenience and efficiency of modern EPROM and EEPROM functions, it is now commonplace to embed non-volatile memory arrays within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logic circuitry. Such embedded non-volatile memories can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, non-volatile memory cells can realize control registers by way of which a larger scale logic circuit can be configured, or can be used to “trim” analog levels after electrical measurement.
As known in the art, “one-time programmable” (“OTP”) memories are also popular, especially in embedded non-volatile memory applications as mentioned above. The memory cells of OTP memories are constructed similarly or identically as UV EPROM cells, and as such are not electrically erasable. But when mounted in an opaque package, without a window through which the memory can be exposed to ultraviolet light, the UV EPROM cells may be programmed one and only one time. In embedded applications, OTP memories are useful for storing the program code to be executed by the embedding microcontroller or microprocessor.
In any type of solid-state semiconductor memory, data path timing for the read operation is critical in the performance of the memory device. As fundamental in the art, memory cells in conventional OTP and other solid-state memories are typically accessed by selecting a row of cells in the array according to a row address, coupling the storage device in each of those cells to a corresponding bit line to establish a voltage or current on each bit line according to the data state stored in its corresponding cell. Sense amplifiers sense the state of the bit lines to determine the data states of the accessed cells, and these sensed data states are then latched and communicated along the output data path of the memory. Accurate sensing of the stored memory cell state must be maintained over varying voltage and temperature conditions, variations in manufacturing parameters, and in the presence of system noise. As known in the art, the noise margin of the read operation, which depends on timing precision in the read circuitry, in large part determines the minimum memory cell size required to provide the necessary read current and thus the memory density in bits per unit “chip” area.
This precision of the sense circuitry is due in large part to the timing at which the sense amplifiers operate to amplify and latch the data state represented by the bit line signals. In each cycle, time must be provided to allow the accessed memory cells to develop a voltage or current on the bit lines, before the amplification and latching of those bit line levels as the data states read from the accessed cells. On one hand, if the data are latched too early in the cycle, before the bit line signal has fully developed, the data read is vulnerable to error from noise. On the other hand, latching the data later than is necessary for reliable sensing will unduly lengthen the read cycle time and thus limit the performance of the device.
It has been observed that the optimization of data path timing for read cycles in modern memory architectures can be quite difficult. One conventional technique for setting the read path timing is to generate a sense amplifier enable signal from a row enable control signal that gates the word line drivers, but with a delay element such as a chain of logic inverters establishing the desired delay time following the driving of the selected word line before the sense amplifiers are enabled or sensed data are latched. It has been observed, however, that the construction and thus the electrical characteristics of the memory cell transistors typically differ from that of the logic transistors making up the delay element. Significant device mismatch can result which, along with localized variations in device behavior of these minimum size cell transistors, necessitates additional design margin (i.e., lengthened delay between the word line drive and the sense amplifier enable signal) to be built into the timing circuit. This additional margin adversely impacts read cycle times.
Another conventional approach to determining sense amplifier timing in modern solid-state memories uses a “tracking” circuit based on replica, or “dummy”, memory cells that are constructed using the same transistor sizes as the cell transistors. This approach is especially common in those memory technologies for which the replica cells can closely match the cell transistors in the main array, such as static random access memories (SRAMs). Arslan et al., “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Custom Integrated Circuits Conference (IEEE, 2008), pp. 415-418, describes the incorporation of a replica column of memory cells implemented in or adjacent to the main memory array, in which the discharge of the replica bit line by a configurable number of dummy memory cells in that column drives the sense amplifier enable signal. Amrutur et al., “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's”, J. Solid State Circuits, Vol. 33, No. 8 (IEEE, 1998), pp. 1208-19, describes a row of replica cells implemented in or adjacent to the main memory array, for which a dummy global word line is driven along with the global word line for the main array.
In some memory architectures, such as those used in conventional one-time-programmable (OTP) memory, the tracking circuit determines the time at which a data latch receiving the output of the sense amplifiers is enabled. In one conventional OTP architecture, the sense amplifier responds asynchronously to the bit line levels to produce an output level that is latched into a read data latch at a point in the cycle determined by the tracking circuit.
FIG. 1 illustrates the functional architecture of a conventional OTP memory including a tracking circuit for timing the latching of the data sensed by sense amplifiers. In this conventional architecture, the OTP bit cells are arranged as rows and columns in main array 2, with the cells in the same row sharing a word line and those in the same column sharing a bit line BL, coupled to a corresponding one of main sense amplifiers 4. Control logic 5 represents timing logic circuitry that generates a word line enable signal WL_EN that gates the row decoder and word line drivers (not shown) to energize the selected word line in main array 2 in the read cycle (indicated by read enable signal READ), at the appropriate time responsive to a clock signal CLK. In the manner discussed above, main sense amplifiers 4 asynchronously sense the state of bit lines BL and present corresponding output signals indicating the sensed data states to read data latches 6. In this conventional OTP architecture, read data latches 6 latch the output data D_OUT presented by main sense amplifiers 4 in response to a LATCH_DATA signal. Tracking circuit 8 also generates a reset signal RESET to control logic 5 at this time, to allow the memory to prepare for the next cycle once the output data are latched at interval t2-t1 from read data latches 6.
According to this conventional OTP architecture, the timing of the LATCH_DATA signal is derived from a tracking circuit 8 that tracks the sensing of a data level stored at one or more replica memory cells 2R following the energizing of the word line enable signal WL_EN. Each replica cell 2R is typically hard-wired to a particular data state, and is coupled to replica bit line RBL as word line enable signal WL_EN is energized. If multiple replica cells 2R are used, these cells 2R are typically ganged together along one or more replica bit lines RBL to minimize the effects of local device variation. Replica sense amplifier 4R issues a signal to tracking circuit 8 in response to a transition at replica bit line RBL. Tracking circuit 8 in turn generates the LATCH_DATA signal, which is (theoretically) at the time that replica sense amplifier 4R produces a stable D_OUT state from the levels at replica bit lines RBL, plus an additional time margin to allow for variation over main array 2. For the reasons discussed above, the timing of this LATCH_DATA signal is critical in the overall performance of this OTP memory. If the LATCH_DATA signal is applied to latches 6 too early in the cycle, the noise margin of the read operation is poor; if it is applied too late in the cycle, the cycle time of the memory is degraded.
It has been observed, however, that conventional tracking circuit approaches are limited in the precision with which sense amplifier or data latch timing can be attained in one-time programmable (OTP) memories. As known in the art, the electrical behavior of OTP memory cells changes over the life of the device, for example because the charge stored at the floating gate of the bit cell transistor leaks or is otherwise weakened. This change in behavior is typically reflected in degradation of the read performance of a programmed (i.e., “1” data state) cell over time. Unfortunately, referring to FIG. 1, replica OTP cells 2R will degrade differently over time than will the average cells in main array 2, if for no other reason because replica cells 2R are accessed in each and every read cycle, while cells in main array 2 are accessed much less frequently, on average.
To avoid the resulting variation in read performance over time, many conventional OTP memories realize replica cells 2R as non-programmable transistors, for example as p-channel MOS load transistors, so that the timing of the LATCH_DATA signal is invariant over the device life. However, the use of different transistor types and arrangements for replica cells 2R from those of the cells in main array 2 results in the tracking circuit and the actual data path exhibiting different behavior over variations in power supply voltage, temperature, and process parameters. FIG. 2a qualitatively illustrates the effect of variations in these parameters on the timing determination in the OTP memory of FIG. 1. In this example of FIG. 2a, plot VBLBC exhibits the bit line voltage VBLBC for a “0” to “1” transition following energizing of the selected word line in main array 2 for a “best case” condition of power supply voltage, temperature, and process parameters. As shown in FIG. 2a, this bit line voltage VBLBC reaches a trip voltage Vtrip at a time t0, at which time the LATCH_DATA signal may be issued to read data latches 6 to accurately latch the output D_OUT of sense amplifiers 4. The “worst case” condition of voltage, temperature, and process on the development of the bit line voltage in this OTP memory is shown by plot VBLWC, which reaches the trip voltage Vtrip at a later time t1.
While the tracking circuit may be arranged to issue the LATCH_DATA signal at any time following worst case time t1, the construction of replica cells 2R from different transistors than the memory cell devices in the main array 2 necessitates the implementation of some timing margin to account for the eventual degradation of the main array cells over system life. Accordingly, the arrangement of replica cells 2R, replica sense amplifier 4R, and tracking circuit 8 in this conventional OTP memory is typically arranged so that the time at which the reference bit line voltage VRBL reaches the trip voltage Vtrip is later than the worst case time t1 for main array 2. FIG. 2a shows an example of this slower development of the reference bit line voltage VRBL, reaching trip voltage Vtrip at time t2.
This margin provided by the interval t2-t1 directly impacts the cycle time of the memory. FIG. 2b illustrates the generation of a stable “1” level at the output D_OUT of sense amplifiers 4 following the issuance of the clock signal CLK to control logic 5 in this architecture. The timing margin indicated by time interval t2-t1, after the worst case time at which the reference bit line voltage VRBL reaches the trip voltage Vtrip, accounts for degradation of the main array cells over device life. In current-day OTP memories, this t2-t1 margin can range from 30 nsec to as much as 100 nsec, depending on memory size. This margin interval t2-t1 can be a significant fraction of the overall cycle time Tcyc of the memory, and thus can affect the overall performance of the device.